1. Field of the Invention
This invention relates to an improved cricuit for latching a state of memory during a power up and reset conditions.
2. Prior Art
The manufacture and use of electrically programmable read only memories (EPROMs) are a well-known technology in the prior art. EPROMs are used in various devices as well as in array structures to provide programmable memories and programmable logic devices.
EPROMs have the capability of storing a change within its cell and to retain the charge for prolonged period of time. When an EPROM has been programmed by having a charge stored in its cell, it is said to have been programmed. When there are no stored charges, the EPROM or is in an unprogrammed or erased state. Because an EPROM is capable of retaining a charge even when power is removed from the circuit, it is capable of retaining a memory state even when the circuit or the device has been deenergized. However, when the device is again energized, the state of the EPROM must be determined before the device is operational.
During the initialization phase when power is applied to a given device, a reset sequence is initiated to determine the various state of the EPROMs of the device. In the prior art, capacitors and other circuits activated the initialization sequence to determine the state of the EPROMs. Typically, these prior art circuits read the state of the EPROMs and latch that state to its respective bit line for processing. However, in most instances the EPROMs were continually being read to provide the information onto the bit line. Typically these power on latching circuits require the reading circuitry to consume power even after the EPROM state had been latched onto a bit line.
It is appreciated that what is needed is an improved circuit to latch the state of a given EPROM yet turning off the EPROM reading circuitry such that power consumption is limited to a minimum value once the reading of the EPROM has been achieved.